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URN etd-0902108-233838 Statistics This thesis had been viewed 3388 times. Download 1099 times. Author Yi-Chia Shan Author's Email Address email@example.com Department Communication Engineering Year 2007 Semester 2 Degree Master Type of Document Master's Thesis Language English Page Count 101 Title ASYNCHRONOUS TWO-DIMENSION DISCRETE COSINE TRANSFORM CIRCUIT DESIGN Keyword DCT Micropipeline Asynchronous Petri-net FPGA FPGA Petri-net Asynchronous Micropipeline DCT Abstract This thesis proposes an asynchronous two-dimension discrete cosine transform (2-D DCT) processor. In asynchronous design, we used Sutherland’s Micropipelines to implement handshake pipeline. In DCT process, we adopt row-column decomposition method to separate 2-D DCT into two one-dimensional discrete cosine transform (1-D DCT) and a transpose memory. In order to realize the matrix calculation easily, multiplier and accumulator method has been adapted.
We implement 2-D DCT function with Field Programable Gate Array (FPGA), and verify the design by the function simulation and timing simulation. FPGA has the programble property, so it’s very convient to be used in design level. We design asynchronous circuit which is based on FPGA architecture. The proposed circuit has asynchronous design spirit, but not completely followed the asynchronous design of the reference paper.
The timing simulation result of 2-D DCT is not satisfied, the reason is related with FPGA architecture and the compile tool. Because we can not control the placement and routing of the circuit very well, the programs are auto compiled by FPGA tool, so it could cause the circuit failed. Although we met many challenges in FPGA design, but these experiences can be refered in the future ASIC asynchronous design.
Advisor Committee Teng-Pin Lin - advisor
Chau-Yun Hsu - co-chair
Ching-Huang Wei - co-chair
Files Date of Defense 2008-07-25 Date of Submission 2008-09-10