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URN etd-0902109-173723 Statistics This thesis had been viewed 2279 times. Download 1230 times. Author Chun-Kai Huang Author's Email Address No Public. Department Computer Science and Enginerring Year 2008 Semester 2 Degree Master Type of Document Master's Thesis Language zh-TW.Big5 Chinese Page Count 62 Title Integrating Self-timed Hardware Accelerators into Nios II Platform Keyword Hardware accelerator Nios II SOPC Self-timed system Asynchronous circuit Asynchronous circuit Self-timed system SOPC Nios II Hardware accelerator Abstract Hardware accelerators are commonly used to speed up some critical operations in embedded system design.
This thesis proposes a new approach to design hardware accelerator which integrates self-timed hardware accelerators into Altera Nios II platform. The self-timed hardware accelerator consists of one self-timed core which is automatically synthesized from C++ or Java specification by using SoCAD tool and a synchronous to asynchronous interface to plug in the self-timed core to Avalon bus of Nios II SoPC platform.
GCD、Summation and RSA are used as examples to carry out the performance evaluation. The experimental results shows that our self-timed hardware accelerator is 1.4/1.5 times, 8.0/1.3 times, 12.3/2.1 times, 20.7/1.1 times faster than Nios II platform without/with C2H hardware accelerator in GCD, non-pipeline Summation, pipeline Summation and RSA examples, respectively.
Advisor Committee Fu-Chiung Cheng - advisor
Chang-Jiu Chen - co-chair
Liang-Teh Lee - co-chair
Files Date of Defense 2009-07-09 Date of Submission 2009-09-03