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The defense date of the thesis is 2014-09-02
The current date is 2019-03-22
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URN etd-0902114-175951 Statistics This thesis had been viewed 812 times. Download 2 times. Author Ching-yang Huang Author's Email Address No Public. Department Computer Science and Enginerring Year 2013 Semester 2 Degree Master Type of Document Master's Thesis Language zh-TW.Big5 Chinese Page Count 48 Title TESTING OF ASYNCHRONOUS QDI FSMs Keyword QDI Asynchronous testing testing Asynchronous QDI Abstract Quasi-Delay Insensitive(QDI) circuits are the most robust circuits that can be built and prevent from PVT (Process, Voltage, Temperature) impact .
This thesis focuses on how to test ROC QDI finite state machines, using the stuck-at fault model. We use D-algorithm to generate patterns for ROC QDI combinational circuits and modified scan chains to scan in the test patterns and scan out outputs to check the correctness of the QDI finite state machines.
Two types of test methods, namely fault-identification and pass-fail approaches are proposed. The former can identify all S@0 and S@1 faults and locate which circuit path containing the faults. The latter can detect if there is any S@0 or S@1 fault inside a chip, and disregard of the location of the fault.
The experimental results show that fault-identification test approach requires additional 40% of the area cost and pass-fail test approach only additional 15% of the area cost.
Advisor Committee Fu-chiung Cheng - advisor
Chang-jiu Chen - co-chair
Shu-chuan Huang - co-chair
Files Date of Defense 2014-07-29 Date of Submission 2014-09-02