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The defense date of the thesis is 2005-09-03
The current date is 2019-04-25
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URN etd-0903105-100918 Statistics This thesis had been viewed 1629 times. Download 9 times. Author Fei-Ming Chang Author's Email Address firstname.lastname@example.org Department Electrical Engineering Year 2004 Semester 2 Degree Master Type of Document Master's Thesis Language English Page Count 67 Title 5.2GHz VERY LOW POWER QVCO WITH BACK-GATE COUPLING Keyword VCO VCO Abstract ABSTRACT
This research mainly focuses on the design of a novel QVCO with properties of low power, low phase noise & compact size. The new topology consists of the semi-complementary cross-coupled pair with advantage of DC re-use and a concept of back-gate coupling, where the back-gates of the core transistors are used as coupling terminals. Through this topology, the 16 transistors of a complementary differential QVCO can be reduced to 4, as well as the decrease of power dissipation and additional noise contribution. A QVCO based on the proposed topology is implemented with TSMC 0.18 μm technology for 5.28G operation and measurement shows the phase noise of -117.758 dBc / Hz @ 1MHz offset with power consumption only 2.86 mW.
Advisor Committee none - advisor
none - co-chair
none - co-chair
Files Date of Defense 2005-07-20 Date of Submission 2005-09-03