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Title page for etd-0903112-104214


URN etd-0903112-104214 Statistics This thesis had been viewed 1779 times. Download 688 times.
Author Wei-Ting Chung
Author's Email Address No Public.
Department Computer Science and Enginerring
Year 2011 Semester 2
Degree Master Type of Document Master's Thesis
Language zh-TW.Big5 Chinese Page Count 94
Title Sorting Unit For FPGA-based System
Keyword
  • sorting
  • hardware design
  • hardware design
  • sorting
  • Abstract As most smartphone use third-party software, so it is necessary to use the database. When it needs to find the required information in the database, this time we need to use the sorting algorithm to sort.
       In this thesis, we propose two algorithms based on Shengnan Dong, Xiaotao Wang, Xingbo Wang their paper, and continue its benefits, component size isn’t limit the Sort quantity.
       Compared with the "A NOVEL HIGH-SPEED PARALLEL SCHEME FOR DATA SORTING ALGORITHM BASED ON FPGA", an architecture can reduce the 2/3 of memory usage and speed up to 2x , another architecture use the original 2/3 of the memory size, but the effect of 3 to 6 times faster..
    Advisor Committee
  • Jong-Jiann Shieh - advisor
  • none - co-chair
  • none - co-chair
  • Files indicate access worldwide
    Date of Defense 2012-07-30 Date of Submission 2012-09-03


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