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Title page for etd-0906111-160147


URN etd-0906111-160147 Statistics This thesis had been viewed 2273 times. Download 1739 times.
Author Chief-min Ho
Author's Email Address No Public.
Department Communication Engineering
Year 2010 Semester 2
Degree Master Type of Document Master's Thesis
Language English Page Count 45
Title FULL ON-CHIP DYNAMIC-BIASING LOW-DROPOUT REGULATOR WITH TRANSIENT-RESPONSE IMPROVEMENT
Keyword
  • dynamic-biasing
  • SOC
  • voltage regulator
  • LDO
  • LDO
  • voltage regulator
  • SOC
  • dynamic-biasing
  • Abstract An output-capacitorless low-dropout voltage regulator with a pair of differentiators circuit is presented in this thesis. The proposed differentiator pair circuit is based on capacitive coupling. The differentiator pair circuit makes use of the quick transient voltage at the LDO output to dynamicly adjust the bias current momentarily. Hence, the transient response of the LDO is significantly enhanced due to the improvement of the slew rate at the gate of the power transistor.
       The proposed differentiator pair circuit is applied to an output-capacitorless LDO implemented in TSMC 0.35um 2p4m CMOS technology. Hspice simulation results show that the LDO consumes 100uA quiescent current. It regulates the output voltage at 2.8V from a 2.9V supply, with dropout voltage of 100mV at the maximum output current of 100mA. The voltage spike and the recovery time of the LDO with the proposed differentiator pair circuit are reduced to about 70mV and 2us , respectively, whereas they are more than 90mV and 15us for the LDO without the differentiator pair circuit.
    Advisor Committee
  • Shu-chuan Huang - advisor
  • none - co-chair
  • Teng-pin Lin - co-chair
  • Files indicate in-campus access immediately and off-campus access at one year
    Date of Defense 2011-07-29 Date of Submission 2011-09-06


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