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Title page for etd-0907110-164516


URN etd-0907110-164516 Statistics This thesis had been viewed 2917 times. Download 6370 times.
Author Li-Fan Hsu
Author's Email Address t750127@hotmail.com
Department Communication Engineering
Year 2009 Semester 2
Degree Master Type of Document Master's Thesis
Language zh-TW.Big5 Chinese Page Count 46
Title ALL DIGITAL PHASE-LOCKED LOOP WITH HIGH RESOLUTION DIGITAL CONTROLLED OSCILLATOR
Keyword
  • ADPLL
  • Phase-Locked Loop
  • Phase-Locked Loop
  • ADPLL
  • Abstract In this thesis, we implement an all digital phase locked loop (ADPLL) with high resolution digital controlled oscillator. We use time to digital converter to quantize phase error and use a high resolution ring oscillator to be the digital controlled oscillator in the circuit. Working frequency ranges for this ADPLL is about 212~366MHz. When reference signal is 5MHz and a multiplication factor of 64, the lock-in time is about 3.5 s. The feasibility and performance of the ADPLL is verified with the MATLAB Simulink.
    Advisor Committee
  • none - advisor
  • none - co-chair
  • none - co-chair
  • Files indicate in-campus access immediately and off-campus access at one year
    Date of Defense 2010-07-30 Date of Submission 2010-09-08


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