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Title page for etd-0910110-023315


URN etd-0910110-023315 Statistics This thesis had been viewed 1952 times. Download 6 times.
Author Chun-Lin Chen
Author's Email Address No Public.
Department Electrical Engineering
Year 2009 Semester 2
Degree Master Type of Document Master's Thesis
Language zh-TW.Big5 Chinese Page Count 46
Title FPGA IMPLEMENTATION OF AES BY THE STATE MACHINE METHOD
Keyword
  • FPGA
  • cryptology
  • AES
  • AES
  • cryptology
  • FPGA
  • Abstract In this thesis, we use FPGA ( ProASIC3 - A3P600, 0.13μm CMOS process, 1.5V power supply ) to design AES-128 by the state machine method. We use Verilog、Actel Libero IDE v9.0、ModelSim Actel 6.5d to design simulate and implement. The number of Gate Counts is 4192.The operating clock rate is 250 MHz. Data throughput is about 63.4 Mbps.
    Advisor Committee
  • Yaw-Fu Jan - advisor
  • Kou-Cheng Hsu - co-chair
  • Ming-Chieh Tsai - co-chair
  • Files indicate in-campus access at 2 years and off-campus access at 8 years
    Date of Defense 2010-07-28 Date of Submission 2010-09-10


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