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The defense date of the thesis is 2014-09-12
The current date is 2019-07-18
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URN etd-0912114-090742 Statistics This thesis had been viewed 893 times. Download 3 times. Author An-hao Peng Author's Email Address No Public. Department Computer Science and Enginerring Year 2013 Semester 2 Degree Master Type of Document Master's Thesis Language zh-TW.Big5 Chinese Page Count 73 Title DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS LOW POWER QDI COMBINATIONAL LOGIC USING 1-OF-2/1-OF-4 CODE Keyword QDI 1-of-4 dual-rail dual-rail 1-of-4 QDI Abstract With technology advances in semiconductor, process, temperature and voltage (PVT) variations become significant in deep submicron design. PVT variations cause delay variations and timing closure problems for synchronous designs. An alternative is to use asynchronous design that can robustly adapt to PVT variations and accommodate timing discrepancies. Among asynchronous design styles, QDI (Quasi-Delay-Insensitive) circuits stand out for its robustness to delay variations, requiring their data to be encoded in a delay-insensitive manner such as dual-rail and 1-of-n codes. Dual-rail QDI logical functions are simple to construct, but 1-of-4 encoded ones may offer the possibility of lower power consumption.
This thesis designs and implements two set 1-of-4 code logic cell library. A methodology to reduce the hardware logic of dual-rail DIMS structure circuit by using these 1-of-4 code logic cell libraries is then proposed. Two set of circuits (i.e. verifiable benchmark circuits and ISCAS-85) are exploited to carry out hardware cost and energy performance evaluation. The results show that firstly, for cell library, the cost reduction is significant; secondly, for any give logic functions, the cost reduction is significant if 1-of-4 code inputs are allowed to use and marginal if dual-rail interfaces for inputs and outputs have to preserve.
Advisor Committee Fu-chiung Cheng - advisor
Files Date of Defense 2014-07-29 Date of Submission 2014-09-12