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Title page for etd-0913118-210816


URN etd-0913118-210816 Statistics This thesis had been viewed 105 times. Download 0 times.
Author Szu-Chun Huang
Author's Email Address szuchun0827@gmail.com
Department Electrical Engineering
Year 2017 Semester 2
Degree Master Type of Document Master's Thesis
Language zh-TW.Big5 Chinese Page Count 58
Title A SUCCESSIVE APPROXIMATION RECURSIVE DIGITAL LOW-DROPOUT VOLTAGE REGULATOR WITH SPEED-UP CONTROL
Keyword
  • hysteresis dual-border controller
  • LDO
  • SAR ADC
  • SAR ADC
  • LDO
  • hysteresis dual-border controller
  • Abstract This thesis presents a digital low-dropout linear regulator with a 7-bit 75-MS/s SAR digital converter. The shift register in the SAR architecture skips some flip-flops according to the proposed logic, which can shorten the comparison time and achieve fast transient response. In addition, a hysteresis dual-border controller is used to divide the SAR architecture into two conditions, reducing the comparison time under steady state conditions. The digital LDO in TSMC 90nm CMOS achieved 0.5-V input and 0.45-V output with 98.44% efficiency at 0.8mA load current.
    Advisor Committee
  • Shu-Chuan Huang - advisor
  • Mei-Ling Yeh - co-chair
  • Ming-Lang Lin - co-chair
  • Files indicate in-campus access at one year and off-campus not accessible
    Date of Defense 2018-07-27 Date of Submission 2018-09-13


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