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The defense date of the thesis is 2008-10-14
The current date is 2019-03-20
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URN etd-1014108-104304 Statistics This thesis had been viewed 2272 times. Download 10 times. Author Huan-Ting Zhou Author's Email Address No Public. Department Electrical Engineering Year 2008 Semester 1 Degree Master Type of Document Master's Thesis Language zh-TW.Big5 Chinese Page Count 74 Title A 8-BIT 50-MS/s CMOS PIPELINE ANALOG TO DIGITAL CONVERTER Keyword ADC Pipeline Pipeline ADC Abstract Many of the applications nowadays utilize the digital signal processing (DSP) to resolve the transmitted information. Therefore, an analog to digital interface is required between the received analog signal and DSP system and portable consumer electronics, the demand for low-power integrated circuits is indispensable. In many types of CMOS analog to digital converter (ADC) architectures, a pipelined architecture can archive good dynamic range performances and the same throughput as the flash ADC due to the pipelined operation in each range. This thesis focuses on the high-speed design of pipelined ADC. In the meanwhile, we try to minimize the power dissipations as well.
In this thesis, an 8-bit 50MHz pipelined A/D converter, with 1.5-bit resolution per stage, has been successfully designed and implemented using the TSMC 0.18μm 1P6M CMOS process. Simulation results show that the designed pipelined ADC can operate at 50MHz with 48.84dB signal- to- noise ratio – conforming to the 7.81-bit accuracy, and the estimated power dissipation is about 105 mw.
Advisor Committee Yaw-Fu Jan - advisor
none - co-chair
none - co-chair
Files Date of Defense 2008-10-06 Date of Submission 2008-10-14