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The defense date of the thesis is 2008-12-11
The current date is 2019-05-24
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URN etd-1211108-132920 Statistics This thesis had been viewed 2579 times. Download 11 times. Author Shih-Sing Huang Author's Email Address No Public. Department Electrical Engineering Year 2008 Semester 1 Degree Master Type of Document Master's Thesis Language zh-TW.Big5 Chinese Page Count 67 Title 10-BIT 40-MS/S PIPELINE ANALOG TO DIGITAL CONVERTER Keyword ADC Pipeline Pipeline ADC Abstract In this thesis, we design a 10-bit 40MSample/s pipelined analog-to-digital converter (ADC) by TSMC 0.18μm 1P6M mixed signal process technology. The supply voltage is 1.8V. The ADC architecture is nine stage pipelined ADC in this design, we adopt 1.5-bit/per stage architecture and a 2-bit flash ADC in the last stage. In order to decrease noise interference, the whole circuit is designed by fully differential structure.
The ADC is simulated by HSPICE using TSMC 0.18μm 1P6M mixed signal process technology. The proposed ADC has the following performances: For 0.5078125MHz sine wave input, the SNR is 57.8dB, the ENOB is 9.32bits, and the power consumption is 117mW at the maximum conversion rate.
Advisor Committee Yaw-Fu Jan - advisor
Kou-Cheng Hsu - co-chair
Ming-Chieh Tsai - co-chair
Files Date of Defense 2008-10-06 Date of Submission 2008-12-11